The present invention relates to the field of circuit simulation, and more precisely to enabling circuit designers to more easily manage model binning.
Circuit designers frequently use devices of different geometries, e.g., length values and width values, in their circuit designs. Device model equations in a SPICE-like simulator describe electrical device behavior using model parameter values that may depend on device geometries and fabrication processes. It is not always possible to adequately describe the behavior of all devices in a design with a single model statement, e.g., a single set of model parameters.
Modeling engineers may instead use a set of simulator model statements that are each deemed valid for a specific process over a specific range of device geometries. Each span of device width and length, for example, for which a particular model is accurate may be termed a “bin”. “Binning” in the field of SPICE modeling and simulation therefore may refer to the process of partitioning a device description into a model group that encompasses different size ranges of design interest. Binning may further include the process of generating and managing these models.
It has become common in the circuit design industry for integrated circuit foundries or others to provide process design kits to circuit designers. A process design kit may include many sets of model parameter values and/or expressions that may be evaluated to determine model parameter values for each corresponding bin. Such expressions may be formulated in terms of process-specific and/or geometry-specific variables. Process design kit suppliers thus characterize devices using model groups to improve overall model fitting accuracy for circuit designers.
In FIG. 1, a group of geometry-related partitions 100 is shown for various length and width ranges (which are not drawn to scale). In this example, a device may have a length (L) between 0.25 μm to 100 μm and a width (W) between 0.25 μm to 100 μm. A modeling engineer or process design kit provider may divide the description of electrical device behavior into multiple bins as shown. In this example, nine models are used (MODEL1 through MODEL9), with one model used per bin. For devices with length values between 1 μm and 10 μm and width values between 10 μm and 100 μm, the MODEL2 bin may be used, etc. In one exemplary commercially available simulator, the bin names (e.g., “MODEL2”) within a model group may be strings as well as numbers.
Some simulators provide an automatic model selection feature that automatically assigns the correct simulator models to devices according to particular device sizes. This feature may simplify the management of model groups. Model selection is automatic for MOSFET models (e.g., BSIM1, BSIM2, BSIM3, etc.) in an exemplary commercially available simulator.
This particular simulator may define model groups in a netlist by using curly braces, e.g., “{ . . . }”, so the automatic model selector may find a specific model in a model group. Every model in the model group may be given a name and the list of its parameters and/or expressions to be evaluated. The device length and width ranges may be specified using the four geometric parameters lmax, lmin, wmax, and wmin for example. The selection criteria to choose a model for a given device instance may be therefore:lmin<=instance_length<lmax and wmin<=instance_width<wmax
For example, when given a netlist comprising a model group definition and a device instance, the simulator may search through the models in the model group and pick the first model whose geometric range satisfies the selection criteria corresponding to the device instance. The corresponding model parameters are then used during simulation.
In FIG. 2, an exemplary MOS model group 200 is shown. Here each of four bin models (pch_simple.1 through pch_simple.4) comprises many model parameter values, provided in this case over multiple netlist lines. For the following device instances:
M0 (nd ng ns nb) pch_simple m=1.0 w=2.5u l=2u
M1 (pd pg ps pb) pch_simple m=1.0 w=4u l=4u
the simulator's automatic model selector selects bin pch_simple.2 for transistor M0 and bin pch_simple.4 for transistor M1 after searching for a bin model meeting the selection criteria. (Note, in this simulator “u” unit notation denotes micrometers.)
For today's small geometry processes, each individual transistor bin model may contain hundreds of parameters. Further, model groups may have forty or more bins, compared to the mere nine shown in FIG. 1. Model parameter expressions may also be quite complex and may depend on additional parameters, such as those relating to fabrication processes. Multiple models may be needed for different device polarities (e.g., NMOS and PMOS), different voltage device capabilities (e.g., low, medium, and high voltage), different leakage current versions (e.g., low and high leakage), and various other factors. Each of these selection dimensions is multiplicative on the overall model count, and therefore the simulator's model selection task may be both slow and memory intensive.
Accordingly, the inventors have developed a novel way to facilitate model binning to more easily manage model information for circuit simulation.